This invention relates to a nonvolatile semiconductor memory device, such as a flash EEPROM.
It is well known that a flash memory uses stacked-gate transistors as memory cells. A NOR flash EEPROM generally uses channel hot electrons in a write operation and FN tunnel current in an erase operation. There have been various methods of erasing data. For example, in an ETOX (EPROM Tunnel Oxide), a type of Intel""s flash memory, an electric field is applied between the floating gate and the source by grounding the gate of a cell and applying a high voltage (about 10 V) to its source, thereby causing FN tunnel current to flow. Moreover, in the negative gate-source erasing method proposed by AMD Corp., a negative voltage (about xe2x88x9210 V) is applied to the gate of a cell in an erase operation and a positive voltage (about 5 V) is applied to its source, thereby causing FN tunnel current to flow between the floating gate and the source.
As the cell size is scaled down, a high voltage applied to the source of a cell in an erase operation becomes a problem. Use of a double diffused structure for the source region can be considered to improve the junction breakdown voltage so that the junction may withstand a high voltage. Specifically, an N+(As) region as the source region is covered with an Nxe2x88x92(P) region, thereby improving the breakdown voltage. The double diffused structure, however, is a factor that prevents the channel length from being scaled down. Specifically, when an Nxe2x88x92 region is formed to secure a sufficient breakdown voltage, the overlap length Yj of the diffused layer and the gate increases. The overlap length Yj is estimated at about 0.2 xcexcm. When the devices are miniaturized further and particularly the coming generation of 0.25 xcexcm or less in size is taken into account, the channel length L including the Yj part is:
L=Leff+0.2 xcexcm greater than  greater than 0.25 xcexcm
where Leff is the effective channel length.
Thus, the channel length has a significantly adverse effect on the reduction of the cell size.
To overcome this problem, a channel erasing method has been developed. In this method, a high voltage is applied between the substrate (=source) and the word line, thereby causing tunnel current to flow between the floating gate and the substrate. Since the substrate and source have the same potential (the source may be in the floating state), there is no need to take into account the junction breakdown voltage of the source, eliminating the necessity of a double diffused structure.
However, since the method has a large capacity between the floating gate and the substrate, a high voltage must be applied between the gate of the cell and the substrate in an erase operation, as compared with the source erasing method. Therefore, the breakdown voltages of the transistors constituting a decode circuit for supplying a specific voltage to the gate of a cell (word line) or a decode circuit for supplying a specific voltage to the substrate become a problem. To avoid this, the voltages at various sections have been considered to prevent the breakdown voltages of those transistors from becoming a problem.
FIGS. 6A, 6B, and 6C show the relationship between the bias voltages supplied to various sections of a memory cell. As shown in FIGS. 6A and 6B, to suppress the breakdown voltage to a lower level, it is desirable that a negative voltage (Vg=xe2x88x928 V) should be applied to the control gate of a cell in an erase operation and a positive high voltage (Vsub=10 V) should be applied to the substrate. In the case of channel erasing, a memory cell MC is formed in a p-type well isolated from a p-type substrate by an n-type well. A substrate voltage Vsub in the cell is supplied to the p-type well and n-type well.
With the method, a decode circuit can be composed of transistors with a breakdown voltage of 10 V. In contrast, an attempt to cause only the control gate or substrate to have resistance to voltage requires transistors with a breakdown voltage of about 20 V. Thus, as the breakdown voltage of the transistor increases, tox. (the film thickness of the oxide film), L (the channel length), and the like must be twice those of a transistor with a breakdown voltage of 10 V. This makes the decode circuit larger. Consequently, the area the decode circuit occupies on the chip is enormous.
FIGS. 7 to 9 show examples of circuits for applying a channel erase bias voltage to various section of a cell.
FIG. 7 shows an example of a row decode circuit (word line driver). In the row decode circuit, a logic circuit 71a decodes address signals in a voltage 0-Vdd system and an Erase signal. The decode output signal from the logic circuit 71a is converted by a level shifter 71b into signals in a voltage VSW, VBB system. The voltage VSW is the high level of the word line and the voltage VBB is the low level of the word line. The output signal of the level shifter 71b is supplied as a voltage VWL to the word line via an inverter circuit 71c acting as a driving circuit.
FIG. 9 shows the voltage VWL on a word line. In this way, the voltage VWL on the word line is set according to the reading, programming, and erasing of the data. The absolute value of each of the voltage VSW, VBB is set at 10 V or less, which satisfies the breakdown condition of the transistors in the decode circuit.
FIG. 8 shows an example of the configuration of the level shifter shown in FIG. 7.
FIG. 10 shows an example of a decode circuit for supplying a potential to a substrate (p-type well) in which a cell array is formed. In the decode circuit, a logic circuit 100a decodes a block address signal and an Erase signal. The decode output signal of the logic circuit 100a is supplied to a level shifter 100b, which converts it into a voltage VH and a signal of the ground level. The voltage VH is, for example, 10 V. The output signal of the level shifter 100b is supplied to a p-type well via an inverter circuit 100c acting as a driving circuit.
A problem encountered in realizing the negative gate channel erasing method will be explained.
FIG. 11 is a sectional view of an n-channel transistor (NMOS), a p-channel transistor (PMOS) and a memory cell (MC) in the decoder. FIG. 12 shows an equivalent circuit of FIG. 11. There are parasitic capacitances C1 to C5 between the n-channel transistor, p-channel transistor, and memory cell. FIG. 13 shows an equivalent circuit of the parasitic capacitances C1 to C5. The parasitic capacitances C1 to C5 are as follows:
C1: a capacitance between the control gate of a memory cell and the substrate (p-type well)=a series capacitance of (a capacitance between the control gate and the floating gate) and (a capacitance between the floating gate and the substrate).
C2: a capacitance between a block substrate (n-type well or p-type well) and the substrate.
C3: a capacitance between the high level in the decoder (n-type well) and the substrate.
C4: a capacitance between the high level (VSW) and low level (VBB) in the decoder.
C5: a capacitance between the low level (VBB) in the decoder and the substrate.
After an erase operation has been completed, this type of nonvolatile semiconductor memory device has to be reset to the state that allows a read operation. Specifically, the voltage VWL on the word line must be changed from xe2x88x928 V to 0 V and the voltage Vwell at the well must be changed from 10 V to 0 V. A problem encountered in resetting the voltage on the word line and the voltage at the well is the order in which the respective nodes are reset.
FIGS. 14 and 15 illustrate how each node is reset after the completion of the erasure, using extreme examples.
FIG. 14 shows operating waveforms in a case where the voltage VWL (VBB=xe2x88x928 V) on the word line is reset earlier than the voltage at the well. When the VWL on the word line changes from xe2x88x928 V to 0 V, the potential Vwell at the well rises because of a capacitance C1 shown in FIG. 11. As shown in FIG. 10, the Vwell is driven by an inverter circuit 100c to which a voltage VH and the ground potential are supplied as a power source. For this reason, as shown in FIGS. 16A and 16B, as the potential Vwell at the well rises, a forward bias from the voltage Vwell to the voltage VH is generated between the diffused layer of the p-channel transistor constituting the inverter circuit 100c and the n-type well.
In this state, in the worst case, a bipolar transistor to whose base the voltage VH is supplied is formed between the diffusion layer to which the voltage Vwell is supplied and the substrate, thereby releasing a lot of holes into the substrate. This can trigger latch-up.
On the other hand, when the voltage VBB changes relatively slow, a rise in the well potential Vwell causes the voltage VH to rise via a p-channel transistor. Since the voltage VH has been set at the maximum voltage 10 V, if the voltage VH rises any further, this causes the breakdown voltage problem of the transistors.
FIG. 15 shows operating waveforms in a case where the well potential is reset earlier than the potential on the word line. FIGS. 17A and 17B show decode circuits for a word line and a well.
In this case, when the Vwell to is reset, the voltage VWL on the word line undershoots because of the capacitance C1 coupling with the well voltage as shown in FIGS. 17A and 17B. In this state, as shown in FIG. 17B, a forward bias develops in the diffused layer of the n-channel transistor in the p-type well, which can give rise to latch-up in the worst case.
On the other hand, when the voltage on the well changes slowly, the voltage VBB is lowered and undershoots. In the case where the voltage VSW-VBB in the row decode circuit is set at about the maximum voltage of 10 V, when the voltage VBB undershoots, this means that the VBB exceeds 10 V. Accordingly, the breakdown voltage of the transistor must be raised.
Both of the above examples are about extreme cases. However, when an attempt is made to reset the voltage VWL and the voltage Vwell at the same time in completing an erase operation, the aforementioned cases never fail to take place, taking into account the internal parasitic capacitances, resistances, other electrical characteristics, and temperature characteristics. Therefore, provision has to be made to prevent a forward bias from developing or the breakdown voltages of the transistors from deteriorating in any case.
It is, accordingly, an object of the present invention to overcome the above disadvantages by providing a nonvolatile semiconductor memory device capable of not only preventing a forward bias between the diffused layer of a transistor and the substrate by a parasitic capacitance in resetting the potential between two nodes having a potential difference higher than the supply voltage, but also avoiding the breakdown voltage problem of the transistor.
The foregoing object is accomplished by providing a semiconductor memory device comprising: a first and a second node which have a potential difference equal to or higher than a supply voltage between them and are connected to each other via a parasitic capacitance; a first switch circuit which is connected between the first and second nodes; a second switch circuit which is connected between the first node and the ground; a third switch circuit which is connected between the second node and the ground; and a control circuit for controlling the first switch circuit.
Furthermore, the foregoing object is accomplished by providing a semiconductor memory device comprising: a memory cell array divided into blocks, each of the blocks including memory cells, word lines and bit lines being connected to these memory cells, and a row decoder for selecting the word lines; a first decoder for supplying the voltage supplied to the word lines to the row decoder; a second decoder for supplying a substrate voltage to a substrate in which the memory cells are formed; a first switch circuit which is connected between a first node to which the substrate voltage is supplied and a second node to which the voltage on the word line is supplied, the first and second nodes being connected to each other via a parasitic capacitance; a second switch circuit which is connected between the second node and the output terminal of the first decoder; and a third switch circuit which is connected between the first node and the output terminal of the second decoder.
Still furthermore, the foregoing object is accomplished by providing a semiconductor memory device comprising: memory cells formed in a well, each of the memory cells including a stacked-gate transistor where a floating gate and a control gate are stacked one on top of the other, a negative voltage being applied to the control gate of each of the memory cells in an erase operation, and the data in each of the memory cells being erased electrically at the same time by applying a positive voltage to the well; a first switch circuit which is connected between a first node for supplying a voltage to the well and a second node for supplying a voltage to the control gate of the memory cell, the first and second nodes being connected to each other via a parasitic capacitance; a second switch circuit which is connected between the first node and the ground; and a third switch circuit which is connected between the second node and the ground.
According to the present invention, there is provided a nonvolatile semiconductor memory device capable of not only preventing a forward bias between the diffused layer of a channel transistor and the substrate by a parasitic capacitance in resetting the potential between two nodes having a potential difference higher than the supply voltage, but also avoiding the breakdown voltage problem of the transistor.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.